Layer 3 Hardware Offloading (L3HW, otherwise known as IP switching or HW routing) allows to offload some router features onto the switch chip. This allows reaching wire speeds when routing packets, which simply would not be possible with the CPU.
Layer 3 Hardware Offloading has been introduced in RouterOS v7.1beta1.
RouterOS v7.1beta2 added the firewall-compatible mode
(l3hw=fw), which allowed running hardware-accelerated L4 stateful firewall on compatible CRS3xx devices.
RouterOS v7.1beta3 should not be used for l3hw.
RouterOS v7.1beta4: both modes (l3hw=yes and l3hw=fw) merged, allowing to run full hardware routing on some ports and firewall-compatible mode on another. Also, l3hw renamed to l3-hw-offloading
|Full Routing Configuration||Firewall-Compatible Configuration|
RouterOS v7.1beta6: all CRS3xx devices received l3hw support.
RouterOS v7.1beta7: variable MTU / Jumbo frame support.
To enable Layer 3 Hardware Offloading, set l3-hw-offloading=yes for the switch:
Layer 3 Hardware Offloading can be configured for each physical switch port. For example:
Note that l3hw settings for switch and ports are different:
=nofor the switch completely disables offloading - all packets will be routed by CPU.
=nofor a switch port only disables hardware routing from/to this particular port. Moreover, the port can still participate in Fastrack connection offloading.
To enable full hardware routing, enable l3hw on all switch ports:
To make all packets go through the CPU first, and offload only the Fasttrack connections, disable l3hw on all ports but keep it enabled on the switch chip itself:
Packets get routed by the hardware only if both source and destination ports have
l3-hw-offloading=yes. If at least one of them has
l3-hw-offloading=no, packets will go through the CPU/Firewall while offloading only the Fasttrack connections.
The next example enables hardware routing on all ports but the upstream port (sfp-sfpplus16). Packets going to/from sfp-sfpplus16 will enter the CPU and, therefore, subject to Firewall/NAT processing.
The existing connections may be unaffected by the
l3-hw-offloading setting change.
It is impossible to use interface lists directly to control
l3-hw-offloading because an interface list may contain virtual interfaces (such as VLAN) while the
l3-hw-offloading setting must be applied to physical switch ports only. For example, if there are two VLAN interfaces (vlan20 and vlan30) running on the same switch port (trunk port), it is impossible to enable hardware routing on vlan20 but keep it disabled on vlan30.
However, an interface list may be used as a port selector. The following example demonstrates how to enable hardware routing on LAN ports (ports that belong to the "LAN" interface list) and disable it on WAN ports:
Please take into account that since interface lists are not used directly in the hardware routing control, modifying the interface list also does not automatically reflect into l3hw changes. For instance, adding a switch port to the "LAN" interface list does not automatically enable
l3-hw-offloading on that. The user has to rerun the above script to apply the changes.
Starting with RouterOS v7.1beta7, it is possible to change MTU on the hardware interfaces. Previously, only the default MTU 1500 was supported by the hardware, but others were processed by the CPU. The hardware supports up to 8 MTU profiles, meaning that the user can set up to 8 different MTU values for interfaces: the default 1500 + seven custom ones.
l3-hw-offloadingwhile changing the MTU/L2MTU values on the interfaces.
Layer 3 hardware processing lies on top of Layer 2 hardware processing. Therefore, L3HW offloading requires L2HW offloading on the underlying interfaces. The latter is enabled by default, but there are some exceptions. For example, CRS3xx devices support only one hardware bridge. If there are multiple bridges, others are processed by the CPU and are not subject to L3HW.
Another example is ACL rules. If a rule redirects traffic to the CPU for software processing, then hardware routing (L3HW) is not triggered:
To make sure that Layer 3 is in sync with Layer 2 on both the software and hardware sides, we recommend disabling L3HW while configuring Layer 2 features. The recommendation applies to the following configuration:
In short, disable
l3-hw-offloading while making changes under
Since L3HW depends on L2HW, and L2HW is the one that does VLAN processing, Inter-VLAN hardware routing requires a hardware bridge underneath. Even if a particular VLAN has only one tagged port member, the latter must be a bridge member. Do not assign a VLAN interface directly on a switch port! Otherwise, L3HW offloading fails and the traffic will get processed by the CPU:
/interface/vlan add interface=ether2 name=vlan20 vlan-id=20
Assign VLAN interface to the bridge instead. This way, VLAN configuration gets offloaded to the hardware, and, with L3HW enabled, the traffic is subject to inter-VLAN hardware routing.
By default, all the routes are participating to be hardware candidate routes. To further fine-tune which traffic to offload, there is an option for each route to disable/enable
For example, if we know that majority of traffic flows to the network where servers are located, we can enable offloading only to that specific destination:
Now only the route to 192.168.3.0/24 has H-flag, indicating that it will be the only one eligible to be selected for HW offloading:
H-flag does not indicate that route is actually HW offloaded, it indicates only that route can be selected to be HW offloaded.
Firewall filter rules have
hw-offload option for Fasttrack, allowing fine-tuning connection offloading. Since the hardware memory for Fasttrack connections is very limited, we can choose what type of connections to offload and, therefore, benefit from near-the-wire-speed traffic. The next example offloads only TCP connections while UDP packets are routed via the CPU and do not occupy HW memory:
This example demonstrates how to benefit from near-to-wire-speed inter-VLAN routing while keeping Firewall and NAT running on the upstream port. Moreover, Fasttrack connections to the upstream port get offloaded to hardware as well, boosting the traffic speed close to wire-level. Inter-VLAN traffic is fully routed by the hardware, not entering the CPU/Firewall, and, therefore, not occupying the hardware memory of Fasttrack connections.
We use the CRS317-1G-16S+ model with the following setup:
Setup interface lists for easy access:
Routing requires dedicated VLAN interfaces. For standard L2 VLAN bridging (without inter-VLAN routing), the next step can be omitted.
Configure management and upstream ports, a basic firewall, NAT, and enable hardware offloading of Fasttrack connections:
At this moment, all routing still is performed by the CPU. Enable hardware routing on the switch chip:
l3-hw-offloading=no) to make this feature work.
=nofor a given switch port. On the switch level,
|IPv4 Unicast Routing||HW||7.1beta1|
|IPv6 Unicast Routing||CPU|
|IPv4 Multicast Routing||CPU|
|IPv6 Multicast Routing||CPU|
/ip/route add dst-address=10.0.99.0/24 type=blackhole
/ip/route add dst-address=10.0.99.0/24 type=prohibit
The hardware is incapable of sending ICMP replies. Therefore the packets must go through the CPU.
|Unreachable routes||CPU||/ip/route add dst-address=10.0.99.0/24 type=unreachable|
/ip/route add dst-address=10.0.0.0/24 gateway=ether1
This works only for directly connected networks. Since HW does not know how to send ARP requests,
|BRIDGE||HW||IP Routing from/to bridge interface||7.1beta1|
|VLAN||HW||Routing between VLAN interfaces||7.1beta1|
|Firewall||FW||Users must choose either HW-accelerated routing or firewall.|
Firewall rules get processed by the CPU. Fasttrack connections get offloaded to HW.
|NAT||FW||NAT rules applied to the offloaded Fasttrack connections get processed by HW too.||7.1beta4|
|MTU||HW||The hardware supports up to 8 MTU profiles.||7.1beta7|
Only the devices listed in the table below support L3 HW Offloading.
Only the devices listed in the table below support L3 HW Offloading.
The devices below are based on Marvell 98DX8xxx, 98DX4xxx switch chips, or the 98DX3257 model.
|Model||Release||IPv4 Routes 1||Nexthops||Fasttrack connections 2,3,4||NAT entries 2|
|CRS317-1G-16S+||7.1beta1||160K - 240K||8K||4.5K||8K 5|
|CRS309-1G-8S+||7.1beta2||16K - 30K||8K||4.5K||8K|
|CRS312-4C+8XG||7.1beta2||16K - 30K||8K||2.25K||8K|
|CRS326-24S+2Q+||7.1beta2||16K - 30K||8K||2.25K||8K|
|CRS354-48G-4S+2Q+||7.1beta4||16K - 30K||8K||2.25K||8K|
1 Depends on the complexity of the routing table. Whole-byte IP prefixes (/8, /16, /24, etc.) occupy less HW space than others (e.g., /22). When the HW route limit is reached, new route entries are ignored by the switch chip! The user should choose the device with HW capability large enough to store all the routes or/and suppress offloading of the routes that do not fit in the HW memory.
2 When the HW limit of Fasttrack or NAT entries is reached, other connections will fall back to the CPU. MikroTik's smart connection offload algorithm ensures that the connections with the most traffic are offloaded to the hardware.
3 Fasttrack connections share the same HW memory with ACL rules. Depending on the complexity, one ACL rule may occupy the memory of 3-6 Fasttrack connections.
4 MPLS shares the HW memory with Fasttrack connections. Moreover, enabling MPLS requires the allocation of the entire memory region, which could store up to 768 (0.75K) Fasttrack connections otherwise. The same applies to Bridge Port Extender. However, MPLS and BPE may use the same memory region, so enabling them both doesn't double the limitation of Fasttrack connections.
5 All NAT entries cannot be used due to the limited amount of Fasttrack connections.
The devices below are based on Marvell 98DX224S, 98DX226S, or 98DX3236 switch chip model. These devices do not support Fasttrack or NAT connection offloading.
|Model||Release||IPv4 Route Prefixes1||Nexthops||ECMP paths per prefix2|
1 Since the total amount of routes that can be offloaded is limited, prefixes with higher netmask are preferred to be forwarded by hardware (e.g /32 /30 /29, etc.), any other prefixes that do not fit in the HW table will be processed by the CPU.
2 If a route has more paths than the hardware ECMP limit (X), only the first X paths get offloaded.